Since semiconductor transistors were first implemented, there has been an ongoing effort to reduce the area that individual transistors take up on an integrated circuit (i.e., “shrink” them), thereby allowing more transistors to fit on the integrated circuit. This trend is one factor that helps manufacturers to produce more powerful integrated circuits that have more functionality than previous generations. Indeed, this is one factor that has helped to usher in the communications age as we know it.
In addition to shrinking the area of individual transistors, in many applications designers also go to great lengths to match the characteristics of various transistors on a single integrated circuit. For example, designers often match transistor geometries (i.e., layouts) so that the different transistors experience similar electrical stresses with respect to surrounding devices. Depending on design constraints, designers may want to match the gains (□), currents delivered (IDS), voltage thresholds (VT), or other transistor characteristics of two or more transistors.
Accordingly, there is an ongoing need for integrated circuits that strike a balance between minimal transistor area and precise matching.